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INTEGRATED CIRCUITS
DATA SHEET
P89C738; P89C739 8-bit Flash microcontrollers
Product specification Supersedes data of 1997 Dec 15 File under Integrated Circuits, IC20 1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
CONTENTS 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 8.1 8.2 8.3 9 9.1 9.2 10 10.1 10.2 10.3 11 12 12.1 12.2 13 13.1 13.2 13.3 13.4 13.5 14 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pin configuration Pin description FUNCTIONAL DESCRIPTION General Instruction set execution MEMORY ORGANIZATION Program memory Internal data memory Addressing INTERRUPT SYSTEM Interrupt Enable Register (IE) Interrupt Priority Register (IP) TIMERS/COUNTERS Timer 0 and Timer 1 Timer 2 Watchdog Timer (T3) I/O FACILITIES FULL DUPLEX SERIAL PORT (UART) The Serial Port operating modes Serial Port Control Register (SCON) REDUCED POWER MODES Idle mode Power-down mode Wake-up from Power-down mode Status of external pins Power Control Register (PCON) OSCILLATOR CIRCUIT 17 18 19 20 21 21.1 21.2 21.3 22 23 23.1 23.2 23.3 24 25 16.7 16.8 16.9 16.10 16.11 16.12 15 15.1 16 16.1 16.2 16.3 16.4 16.5 16.6 RESET
P89C738; P89C739
Power-on reset MULTIPLE PROGRAMMING ROM (MTP-ROM) Features General description Automatic programming and Automatic chip erase Command definitions Silicon-ID-Read command Set-up of Automatic chip erase and Automatic erase commands Set-up of the Automatic program and Program commands Reset command Write operation status Write operation System considerations Command programming/data programming and erase operation SPECIAL FUNCTION REGISTERS OVERVIEW INSTRUCTION SET LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS Serial Port characteristics Timing waveforms Timing symbol naming conventions PACKAGE OUTLINES SOLDERING Introduction DIP PLCC and QFP DEFINITIONS LIFE SUPPORT APPLICATIONS
1998 Apr 07
2
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
1 FEATURES
P89C738; P89C739
* Frequency range: 3.5 to 40 MHz * ROM code protection. 2 GENERAL DESCRIPTION
* 80C51 CPU * 64-kbyte on-chip Multiple Programming ROM (MTP-ROM), expandable externally to 64 kbytes program memory address space * 512-byte on-chip RAM, expandable externally to 64 kbytes data memory address space * P89C738 pin outs fully compatible to the standard 8051/8052 * 8-bit I/O ports for P89C738: 4 and P89C739: 6 * Full-duplex UART compatible with the standard 80C51 and the 8052 * Two standard 16-bit timers/event counters * An additional 16-bit timer (functionally equivalent to the Timer 2 of the 8052) * On-chip Watchdog Timer (T3) * 6-source and 6-vector interrupt structure with 2 priority levels * Up to 3 external interrupt request inputs * Two programmable power reduction modes: Idle and Power-down * Termination of Idle mode by any interrupt, external or Watchdog Timer reset * Wake-up from Power-down by external interrupt, external or Watchdog Timer reset * Packages, - P89C738: DIP40, PLCC44 and QFP44 - P89C739: PLCC68 and QFP64 * Improved Electromagnetic Compatibility (EMC) 3 ORDERING INFORMATION TYPE NUMBER(1) P89C738ABA P89C738ABP P89C738ABB P89C739ABA P89C739ABB Notes
The P89C738 and P89C739 (hereafter generally referred to as P89C738 unless the P89C739 is specifically mentioned) are 8 8-bit Flash microcontrollers manufactured in an advanced CMOS process and is a derivative of the PCB80C51 microcontroller family. This device provides architectural enhancements that make it applicable in a variety of applications in general control systems, especially in those systems which need a large on-chip ROM and RAM capacity. The P89C738 contains a non-volatile 64-kbyte Multiple Programming ROM (MTP-ROM) program memory, a volatile 512 bytes read/write data memory, four 8-bit I/O ports (six for the P89C739), two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the Timer 2 of the 8052), a multi-source two-priority-level nested interrupt structure, one serial interface (UART), a Watchdog Timer (T3), an on-chip oscillator and timing circuits. For systems that require extra capability, the P89C738 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The P89C738 has the same instruction set as the PCB80C51 which consists of over 100 instructions: 49 one-byte, 46 two-byte and 16 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 750 ns and 40% in 1.5 s. Multiply and divide instructions require 3 s.
PACKAGE NAME PLCC44 DIP40 QFP44 PLCC68 QFP64 DESCRIPTION plastic leaded chip carrier; 44 leads plastic dual in-line package; 40 leads (600 mil) plastic quad flat package; 44 leads plastic leaded chip carrier; 68 leads plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height VERSION note 2 SOT129-1 note 2 note 2 SOT319-1
1. Temperature and frequency range for all types: 0 to 70 C and 3.5 to 40 MHz. 2. For more information on the package outline of this version, please contact the Philips Semiconductors Sales office.
1998 Apr 07
3
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dbook, full pagewidth
1998 Apr 07
XTAL1 XTAL2
4
Philips Semiconductors
8-bit Flash microcontrollers
BLOCK DIAGRAM
T0 (2) T1 (2)
INT0 (2) INT1 (2) internal interrupts
VDD
VSS
RXD (2) TXD (2)
TWO 16-BIT TIMERS/ EVENT COUNTERS (T0, T1) 80C51 core excluding ROM/RAM
CPU
PROGRAM MEMORY 64-kbyte MTP-ROM
DATA MEMORY 256-byte RAM
DATA MEMORY 256-byte AUX-RAM
PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT
P89C738 P89C739
8-bit internal bus
PARALLEL I/O PORTS AND EXTERNAL BUS
16 kbytes BUS EXPANSION CONTROL
16-BIT TIMER/ EVENT COUNTER (T2)
4
8 P0
WATCHDOG TIMER (T3)
8
8
8
8
8
internal reset WR (2) T2EX (1) T2 (1)
P1
P2
P3
P4(3) P5(3)
PSEN EA
ALE/WE
RST
MGK189
RD (2)
P89C738; P89C739
Product specification
(1) Alternative function for Port 1. (2) Alternative function for Port 3. (3) P4 and P5 are only available on the P89C738ABA and P89C739ABB (PLCC68 and QFP64).
Fig.1 Block diagram.
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
5 FUNCTIONAL DIAGRAM
P89C738; P89C739
handbook, full pagewidth
XTAL1 ADDRESS AND DATA BUS
PORT 0
XTAL2
RST EA PSEN ALE PORT 1
T2 T2EX
P89C738 P89C739
PORT 5 PORT 2 ADDRESS BUS
RXD TXD INT0 INT1 T0 T1 WR RD VSS VDD
MGK191
PORT 4
PORT 3
secondary functions
Fig.2 Functional diagram.
1998 Apr 07
5
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
6 6.1 PINNING INFORMATION Pin configuration
P89C738; P89C739
43 P0.0/AD0
42 P0.1/AD1
41 P0.2/AD2
P1.5 7 P1.6 8 P1.7 9 RST 10 P3.0/RXD/data 11 n.c. 12 P3.1/TXD/clock 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/T1 17
40 P0.3/AD3
handbook, full pagewidth
3 P1.1/T2EX
2 P1.0/T2
44 VDD
6 P1.4
5 P1.3
4 P1.2
1 n.c.
39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA/VPP
P89C738ABA
34 n.c. 33 ALE/WE 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13
P2.3/A11 27
XTAL1 21
VSS 22
n.c. 23
P2.0/A8 24
P2.1/A9 25
P2.2/A10 26
P2.4/A12 28
P3.6/WR 18
P3.7/RD 19
XTAL2 20
MGK185
Fig.3 Pin configuration for PLCC44 package; for more information on the version see Chapter 3.
1998 Apr 07
6
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, halfpage
P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST
1 2 3 4 5 6 7 8 9
40 VDD 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/VPP 30 ALE/WE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
MGK184
P3.0/RXD/data 10
P89C738ABP
P3.1/TXD/clock 11 P3.2/INT0 12 P3.3/INT1 13 P3.4/T0 14 P3.5/T1 15 P3.6/WR 16 P3.7/RD 17 XTAL2 18 XTAL1 19 VSS 20
Fig.4 Pin configuration for DIP40 package (SOT129-1).
1998 Apr 07
7
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
43 P3.7/RD
37 P2.1/A9
38 P2.0/A8
42 XTAL2
41 XTAL1
handbook, full pagewidth
34 P2.4/A12
36 P2.2/A10
35 P2.3/A11
44 P3.6/WR
40 VSS
39 n.c.
P1.5 1 P1.6 2 P1.7 3 RST 4 P3.0/RXD/data 5 n.c. 6 P3.1/TXD/clock 7 P3.2/INT0 8 P3.3/INT1 9 P3.4/T0 10 P3.5/T1 11
33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA/VPP
P89C738ABB
28 n.c. 27 ALE/WE 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13
P0.2/AD2 21
P1.1/T2EX 15
P0.3/AD3 22
P1.4 12
P1.3 13
P1.2 14
P1.0/T2 16
n.c. 17
VDD 18
P0.0/AD0 19
P0.1/AD1 20
MGK186
Fig.5 Pin configuration for QFP44 package; for more information on the version see Chapter 3.
1998 Apr 07
8
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
65 P2.7/AD15
64 P2.6/AD14
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
68 ALE/WE
handbook, full pagewidth
P5.5 10 P0.3/AD3 11 P0.2/AD2 12 P5.6 13 P0.1/AD1 14 P0.0/AD0 15 P5.7 16 VDD 17 n.c. 18 P1.0/T2 19 P4.0 20 P1.1/T2EX 21 P1.2 22 P1.3 23 P4.1 24 P1.4 25 P4.2 26
61 P2.5/AD13
EA/VPP
67 PSEN
P5.4
P5.3
63 P5.2
62 P5.1
n.c.
n.c.
66 n.c.
9
8
7
6
5
4
3
2
1
60 P5.0 59 P2.4/AD12 58 P2.3/AD11 57 P4.7 56 P2.2/AD10 55 P2.1/AD9 54 P2.0/AD8 53 P4.6
P89C739ABA
52 n.c. 51 VSS 50 P4.5 49 XTAL1 48 XTAL2 47 P3.7/RD 46 P4.4 45 P3.6/WR 44 P4.3
P1.5 27
P1.6 28
P1.7 29
RST 30
n.c. 31
n.c. 32
n.c. 33
P3.0/RXD/data 34
n.c. 35
n.c. 36
n.c. 37
n.c. 38
P3.1/TXD/clock 39
P3.2/INT0 40
P3.3/INT1 41
P3.4/T0 42
P3.5/T1 43
MGK187
Fig.6 Pin configuration for PLCC68 package; for more information on the version see Chapter 3.
1998 Apr 07
9
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
55 P2.7/AD15
60 P0.7/AD7
62 P0.5/AD5
61 P0.6/AD6
57 ALE/WE
handbook, full pagewidth
54 P2.6/AD14
59 EA/VPP
56 PSEN
63 P5.3
64 P5.4
P0.4/AD4 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VDD
1 2 3 4 5 6 7 8 9
52 P5.1 51 P2.5/AD13 50 P5.0 49 P2.4/AD12 48 P2.3/AD11 47 P4.7 46 P2.2/AD10 45 P2.1/AD9 44 P2.0/AD8 43 P4.6 42 n.c. 41 VSS 40 P4.5 39 XTAL1 38 XTAL2 37 P3.7/RD 36 P4.4 35 P3.6/WR 34 P4.3 33 P3.5/T1 P3.4/T0 32
VSS 10 P1.0/T2 11 P4.0 12 P1.1/T2EX 13 P1.2 14 P1.3 15 P4.1 16 P1.4 17 P4.2 18 P1.5 19 P1.6 20 P1.7 21 RST 22 n.c. 23 n.c. 24
P89C739ABB
n.c. 25
P3.0/RXD/data 26
n.c. 27
n.c. 28
P3.1/TXD/clock 29
P3.2/INT0 30
P3.3/INT1 31
53 P5.2
58 n.c.
MGK188
Fig.7 Pin configuration for QFP64 package (SOT319-1).
1998 Apr 07
10
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8-bit Flash microcontrollers
P3.0/RXD/data P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6WR P3.7/RD
34 40 41 42 43 45 47
26 29 30 31 32 33 35 37
5 7 8 9 10 11 44 43
11 13 14 15 16 17 18 19
10 11 12 13 14 15 16 17
P3.1/TXD/clock 39
P89C738; P89C739
XTAL2
48
38
42
20
18
Product specification
XTAL1
49
39
41
21
19
VSS
51
41
40
22
20
1998 Apr 07 12
Philips Semiconductors
PIN(1) SYMBOL PLCC68 P2.0/A8 to P2.2/A10 P2.3/A11 to P2.4/A12 P2.5/A13 to P2.7/A15 PSEN 54 to 56 58 to 59 61, 64 and 65 67 QFP64 44 to 46 48 to 49 51, 54 and 55 56 23 to 25 26 32 29 PLCC44 38 to 34 QFP44 24 to 31 DIP40 21 to 28 Port 2: P2.0 to P2.7; 8-bit quasi-bidirectional I/O Port with internal pull-ups. Port 2 can sink/source one TTL (= 4 LSTTL) input. It can drive CMOS inputs without external pull-ups. Port 2 alternative functions are: A8 to A15; during access to external memories (RAM/ROM) that use 16-bit addresses (MOVX @DPTR) Port 2 emits the high-order address byte (A8 to A15). Program Store Enable output: read strobe to the external program memory via Port 0 and Port 2. It is activated twice each machine cycle during fetches from external program memory. When executing out of external program memory two activations of PSEN are skipped during each access to external data memory. PSEN is not activated (remains HIGH) during no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs. It can drive CMOS inputs without external pull-ups. Address Latch Enable output: latches the lower byte of the address during access to external memory in normal operation. It is activated every six oscillator periods except during an external data memory access. ALE can sink/source 8 LSTTL inputs. It can drive CMOS inputs without an external pull-up. WE: Write Enable. EA/VPP 2 59 29 35 31 External Access input: when during reset, EA is held at a TTL HIGH level, the CPU executes from the internal program ROM. When EA is held at a TTL LOW level during reset, the CPU executes out of external program memory via Port 0 and Port 2. EA is not allowed to float. EA is latched during reset and don't care after reset. DESCRIPTION
8-bit Flash microcontrollers
ALE/WE(2)
68
57
27
33
30
P89C738; P89C739
VPP: programming supply voltage. P0.7/AD7 to P0.4/AD4 P0.3/AD3 to P0.2/AD2 P0.1/AD1 to P0.0/AD0 VDD 3, 5, 6 and 9 11 to 12 14 to 15 17 60, 61, 62 30 to 33 and 1 3 to 4 6 to 7 9 22 to 21 20 to 19 18 44 40 Power supply (+5 V) pin for normal operation, Idle mode and Power-down mode. 36 to 43 32 to 39 Port 0: P0.7 to P0.0; 8-bit open-drain bidirectional I/O port. It is also the multiplexed low-order address and data bus during accesses to external memory: AD0 to AD7. During these accesses internal pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
Product specification
1998 Apr 07 13
Philips Semiconductors
PIN(1) SYMBOL PLCC68 P4.0 to P4.7 20, 24, 26, 44, 46, 50, 53 and 57 60, 62, 63, 7, 8, 10, 13 and 16 1, 4, 18, 31, 32, 33, 35, 36, 37, 38 52 and 66 QFP64 PLCC44 QFP44 n.a. DIP40 n.a. Port 4: P4.0 to P4.7; 8-bit quasi-bidirectional I/O port with internal pull-ups. Port 4 can sink/source 4 LSTTL inputs. It can drive CMOS inputs without external pull-ups. Port 5: P5.0 to P5.7; 8-bit quasi-bidirectional I/O port with internal pull-ups. Port 5 can sink/source 4 LSTTL inputs. It can drive CMOS inputs without external pull-ups. Not connected. 12, 16, n.a.(3) 18, 34, 36, 40, 43 and 47 50, 52, 53, 63, 64, 2, 5 and 8 23, 24, 25, 27, 28, 42 and 58 n.a. DESCRIPTION
8-bit Flash microcontrollers
P5.0 to P5.7
n.a.
n.a.
n.c.
6, 17, 28 and 39
1, 12, 23 and 34
n.a.
Notes 1. To avoid a `latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than VDD + 0.5 V or lower than VSS - 0.5 V respectively. 2. To prohibit the toggling of the ALE/WE pin (RFI noise reduction) the bit RFI in the PCON register (PCON.5) must be set by software. This bit is cleared on reset and can be cleared by software. When set, ALE/WE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE/WE as a normal MOVX. ALE/WE will retain its normal HIGH value during Idle mode and a LOW value during Power-down mode while in the `RFI' mode. Additionally during internal access (EA = 1) ALE/WE will toggle normally when the address exceeds the internal program memory size. During external access (EA = 0) ALE/WE will always toggle normally, whether the flag `RFI' is set or not. 3. n.a. = not applicable.
P89C738; P89C739
Product specification
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
7 FUNCTIONAL DESCRIPTION
P89C738; P89C739
The P89C738 has two software selectable modes of reduced activity for further power reduction: Idle and Power-down. The Idle mode freezes the CPU while allowing the RAM, timers, serial ports and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative except the Watchdog Timer if it is enabled. The Power-down mode can be terminated by an external reset, a Watchdog Timer overflow and in addition, by either of the two external interrupts. 7.2 Instruction set execution
This chapter gives a brief overview of the device. Detailed functional descriptions are given in the following chapters: Chapter 8 "Memory organization" Chapter 9 "Interrupt system" Chapter 10 "Timers/counters" Chapter 11 "I/O facilities" Chapter 12 "Full duplex Serial Port (UART)" Chapter 13 "Reduced power modes" Chapter 14 "Oscillator circuit" Chapter 15 "Reset" Chapter 16 "Multiple Programming ROM (MTP-ROM)". 7.1 General
The P89C738 is a stand-alone high-performance microcontroller designed for use in real time applications such as instrumentation, industrial control and medium to high-end consumer applications. In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these applications. The P89C738 is a control-oriented CPU with on-chip Program and data memory. It can execute programs with internal or external program memory up to 64 kbytes. It can also access up to 64 kbytes of external data memory. For systems requiring extra capability, the P89C738 can be expanded using standard memories and peripherals.
The P89C738 uses the powerful instruction set of the 80C51. Additional Special Function Registers (SFRs) are incorporated to control the on-chip peripherals. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 16 MHz oscillator, 64 instructions execute in 750 ns and 45 instructions execute in 1.5 s. Multiply and divide instructions execute in 3 s (see Chapter 18).
1998 Apr 07
14
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
8 MEMORY ORGANIZATION 8.2
P89C738; P89C739
Internal data memory
The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 64 kbytes external data memory (of which the lower 256 bytes reside in the internal AUX-RAM), 512 bytes internal data memory (consisting of 256 bytes standard RAM and 256 bytes AUX-RAM) and the 64 kbytes internal and external program memory. 8.1 Program memory
The internal data memory is divided into three physically separated parts: 256 bytes of RAM, 256 bytes of AUX-RAM, and a 128 bytes Special Function Registers (SFRs) area. These parts can be addressed as follows (see Fig.9 and Table 3): * RAM locations 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. * RAM locations 128 to 255 can only be addressed indirectly. Address pointers are R0 and R1 of the selected register bank. * AUX-RAM locations 0 to 255 are indirectly addressable as the external data memory locations 0 to 255 with the MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. When executing from internal program memory, an access to AUX-RAM 0 to 255 will not affect the ports Port 0, Port 2, P3.6 and P3.7. * The SFRs can only be addressed directly in the address range from 128 to 255. An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 80C51 structure, i.e. with Port 0 and Port 2 as data/address bus and P3.6 and P3.7 as write and read timing signals. Note that the external data memory cannot be accessed with R0 and R1 as address pointer. Figure 9 shows the internal and external data memory address space. Chapter 17 shows the Special Function Registers overview. Four 8-bit register banks occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal 256-byte RAM. The stack depth is only limited by the available internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-bit register banks reside in the SFR address space. Table 3 Internal data memory access LOCATION 0 to 127 128 to 255 SFR 128 to 255 0 to 255 AUX-RAM ADDRESS MODE direct and indirect indirect only direct only indirect only with MOVX
The program memory address space of the P89C738 comprises an internal and an external memory portion. The P89C738 has 64 kbytes of program memory on-chip. The program memory can also be externally addressed up to 64 kbytes. If the EA pin is held HIGH, the P89C738 executes out of the internal program memory. If EA pin is held LOW, the P89C738 fetches all instructions from the external program memory. Figure 8 illustrates the program memory address space. The security bit is always set in the P89C738 and P89C739 to protect the ROM code. Table 2 lists the access to the internal and external program memory by the MOVC instructions when the security bit has been set to a logic 1. If the security bit has been set to a logic 0 there are no restrictions for the MOVC instructions. Table 2 Internal and external program memory access PROGRAM MEMORY ACCESS INTERNAL YES NO EXTERNAL YES YES
MOVC INSTRUCTION MOVC in internal program memory MOVC in external program memory
65535 handbook, halfpage
INTERNAL (EA = 1)
EXTERNAL (EA = 0)
0
MGK190
MEMORY RAM
PROGRAM MEMORY
Fig.8 Program memory address space.
1998 Apr 07
15
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, full pagewidth 64 kbytes
64 kbytes
64 kbytes
INTERNAL (EA = 1)
EXTERNAL (EA = 0)
OVERLAPPED SPACE 256 255 INDIRECT ONLY 127 DIRECT AND INDIRECT 0 0 MAIN RAM SFRs AUXILIARY RAM
PROGRAM MEMORY
INTERNAL DATA MEMORY
MBK524
EXTERNAL DATA MEMORY
Fig.9 Internal and external data memory address space.
8.3
Addressing
The P89C738 has five modes for addressing: * Register * Direct * Register-Indirect * Immediate * Base-Register plus Index-Register-Indirect. The first three methods can be used for addressing destination operands. Most instructions have a `destination/source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Access to memory addresses is as follows: * Register in one of the four 8-bit register banks through Register, Direct or Register-Indirect addressing
* 512 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0 to 127 of internal RAM may be addressed directly/indirectly. Bytes 128 to 255 of internal RAM share their address location with the SFRs and so may only be addressed indirectly as data RAM. Bytes 0 to 255 of AUX-RAM can only be addressed indirectly via MOVX. * SFR through Direct addressing at address locations 128 to 255 * External data memory through Register-Indirect addressing * Program memory look-up tables through Base-Register plus Index-Register-Indirect addressing.
1998 Apr 07
16
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
9 INTERRUPT SYSTEM Table 4
P89C738; P89C739
Interrupt vectors PRIORITY WITHIN LEVEL 1 (highest) 2 3 4 5 6 (lowest) VECTOR ADDRESS 0003H 000BH 0013H 001BH 0023H 002BH
The P89C738 contains the same interrupt structure as the PCB80C51BH, but with a six-source interrupt structure with two priority levels (see Fig.10). The external interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in SFR TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to, only if the interrupt was transition-activated. If the interrupt was level-activated the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. The Timer 0 and Timer 1 interrupts are generated by TF0 and TF1, which are set by a roll-over in their respective timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. The Serial Port interrupt is generated by the logical `OR' of RI and TI. Neither of these flags is cleared by hardware. The service routine will normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared by software. The Timer 2 interrupt is generated by the logical OR of TF2 and EXF2. Neither of these flags is cleared by hardware. In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software. An additional (third) external interrupt is available, if Timer 2 is not used as timer/counter or if Timer 2 is used in the baud rate generator mode. That external interrupt 2 is falling-edge triggered. It shares the Timer 2 interrupt vector, interrupt enable and interrupt priority bits. If bit EXEN2 = 1 (T2CON.3), a HIGH-to-LOW transition at pin P1.1/T2EX sets the interrupt request flag EXF2 (T2CON.6) and can be used to generate an external interrupt. The interrupt vectors are listed in Table 4.
SOURCE IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2
handbook, halfpage
0 INT0 1 IT0 IE0
TF0
0 INT1 1 IT1 IE1
interrupt sources
TF1 TI RI TF2 EXF2
MGK193
Fig.10 P89C738/P89C739 interrupt sources.
1998 Apr 07
17
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
9.1 Interrupt Enable Register (IE) Interrupt Enable Register (SFR address A8H) 6 - Description of IE bits SYMBOL EA - ET2 ES ET1 EX1 ET0 EX0 DESCRIPTION 5 ET2 4 ES 3 ET1 2 EX1
P89C738; P89C739
Table 5 7 EA Table 6 BIT 7 6 5 4 3 2 1 0 9.2
1 ET0
0 EX0
General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any individually enabled interrupt will be accepted. reserved enable Timer 2 interrupt enable Serial Port interrupt enable Timer 1 interrupt enable external interrupt 1 enable Timer 0 interrupt enable external interrupt 0
Interrupt Priority Register (IP) Interrupt Priority Register (SFR address B8H) 6 - Description of IP bits SYMBOL - - PT2 PS PT1 PX1 PT0 PX0 reserved reserved Timer 2 interrupt priority level Serial Port interrupt priority level Timer 1 interrupt priority level external interrupt 1 priority level Timer 0 interrupt priority level external interrupt 0 priority level DESCRIPTION 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
Table 7 7 - Table 8 BIT 7 6 5 4 3 2 1 0
1998 Apr 07
18
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
10 TIMERS/COUNTERS The P89C738 contains three 16-bit timer/counters: Timer 0, Timer 1 and Timer 2; and one 8-bit timer, the Watchdog Timer (T3). Timer 0, Timer 1 and Timer 2 may be programmed to carry out the following functions: * Measure time intervals and pulse durations * Count events * Generate interrupt requests. 10.1 Timer 0 and Timer 1
P89C738; P89C739
Timer 0 and Timer 1 can be programmed independently to operate in one of four modes: Mode 0 8-bit timer/counter with divide-by-32 prescaler Mode 1 16-bit timer/counter Mode 2 8-bit timer/counter with automatic reload Mode 3 Timer 0: one 8-bit timer/counter and one 8-bit timer. Timer 1: stopped. When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port transmission-rate generator. With a 16 MHz crystal, the counting frequency of these timer/counters is as follows: * In the timer function, the timer is incremented at a frequency of 1.33 MHz (112 x oscillator frequency) * In the counter function, the frequency handling range for external inputs is 0 to 0.66 MHz. Both internal and external inputs can be gated to the timer by a second external source for directly measuring pulse duration. The timers are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3 as previously described.
Timers 0 and 1 each have a control bit in SFR TMOD that selects the timer or counter function of the corresponding timer. In the timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 112 of the oscillator frequency. In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. 10.1.1 Table 9 7 GATE Timer/Counter Mode Control Register (TMOD)
Timer/Counter Mode Control Register (SFR address 89H) 6 C/T 5 M1 4 M0 3 GATE 2 C/T 1 M1 0 M0
Table 10 Description of TMOD bits for Timer 1 and Timer 0 Timer 0: bit TMOD.0 to TMOD.3; Timer 1: bit TMOD.4 to TMOD.7; n = 0, 1. BIT 7 and 3 SYMBOL GATE DESCRIPTION Gating control. When set Timer/counter `n' is enabled only when INTn pin is HIGH and control bit TRn (TR1 or TR0) is set. When cleared Timer n is enabled whenever TRn control bit is set. Timer or Counter Selector. Cleared for Timer operation; input from internal system clock. Set for Counter operation; input from pin Tn (T1 or T0). Timer 0, Timer 1 mode select; see Table 11.
6 and 2 5 and 1 4 and 0
C/T M1 M0
1998 Apr 07
19
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
Table 11 Timer 0; Timer 1 mode select M1 0 0 1 1 1 10.1.2 M0 0 1 0 1 1 OPERATING Timer TL0; TL1 serves as 5-bit prescaler.
P89C738; P89C739
16-bit Timer/Counter TH0; TH1 and TL0; TL1 are cascaded; there is no prescaler. 8-bit auto-reload Timer/Counter TH0; TH1 holds a value which is to be reloaded into TL0; TL1 each time it overflows. Timer 0: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. Timer 1: Timer/Counter 1 stopped.
Timer/Counter Control Register (TCON)
Table 12 Timer/Counter Control Register (SFR address 88H) 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
Table 13 Description of TCON bits BIT 7 and 5 6 and 4 3 and 1 2 and 0 SYMBOL DESCRIPTION
TF1 and TF0 Timer 1 and Timer 0 overflow flags. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR1 and TR0 Timer 1 and Timer 0 run control bits. Set/cleared by software to turn Timer/Counter on/off. IE1 and IE0 IT1 and IT0 Interrupt 1 and Interrupt 0 edge flags. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 and Interrupt 0 type control bits. Set/cleared by software to specify falling edge/LOW level triggered external interrupts.
1998 Apr 07
20
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
10.2 Timer 2
P89C738; P89C739
Timer 2 is functionally similar to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter which is formed by two SFRs, TL2 and TH2. Another pair of SFRs, RCAP2L and RCAP2H, form a 16-bit capture register or a 16-bit reload register. Like Timer 0 and Timer 1, Timer 2 can operate either as timer or as event counter. This is selected by bit C/T2 in SFR T2CON. The timer has three operating modes: `capture', `autoload' and `baud rate generator', which are selected by bits in SFR T2CON (see Tables 14 and 15). 10.2.1 TIMER/COUNTER 2 CONTROL REGISTER (T2CON)
Table 14 Timer/Counter 2 Control Register (SFR address C8H) 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2
Table 15 Description of T2CON bits BIT 7 SYMBOL TF2 DESCRIPTION Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. When Timer 2 interrupt is enabled, TF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. Timer 2 external flag. Set when either a capture or reload is caused by a negative transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX, if Timer 2 is not being used to clock the Serial Port. EXEN2 = 0, causes Timer 2 to ignore events at T2EX. Timer 2 start/stop control. TR2 = 1 starts Timer 2; TR2 = 0 stops Timer 2. Timer 2 timer or counter select. C/T2 = 0 selects the internal timer with a clock frequency of 112fclk. C/T2 = 1 selects the external event counter; falling edge triggered. Capture/reload flag. When set, capture will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, reloads will occur upon either Timer 2 overflows or negative transitions at T2EX if EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to reload upon overflow.
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2 1 0
TR2 C/T2 CP/RL2
Table 16 Timer 2 operating modes X = don't care. RCLK 0 0 1 X 1998 Apr 07 TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 16-bit automatic reload 16-bit capture baud rate generator off 21 MODE
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
10.2.2 CAPTURE MODE
P89C738; P89C739
The baud rate generation by Timer 1 and/or Timer 2 is used for the Serial Port in Mode 1 and Mode 3. The baud rate generation mode is similar to the automatic reload mode, in that a roll-over in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. The baud rates for the Serial Port in Modes 1 and 3 are determined by Timer 2 overflow rate as follows: Timer 2 overflow rate Baud rate = ------------------------------------------------------16 Timer 2 can be configured for either `timer' or `counter' operation. Normally, as a timer it would increment every machine cycle (thus at 112fclk). As a baud rate generator, however it increments every state time (thus at 12fclk). The baud rate is given by the formula: f clk Baud rate = --------------------------------------------------------------------------------------------------32 x [ 65536 - ( RCAP2H, RCAP2L ) ] In this mode an overflow of Timer 2 does not set TF2. If EXEN2 = 1, a HIGH-to-LOW transition at pin T2EX sets EXF2 and can be used to generate an interrupt.
In the capture mode (see Fig.11) there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer/counter which on overflow sets bit TF2 (Timer 2 overflow bit). TF2 can be used to generate an interrupt. If EXEN2 = 1, Timer 2 operates as above, with the added feature that a HIGH-to-LOW transition at the external input T2EX causes the current value in Timer 2 registers (TL2 and TH2) to be captured into registers RCAP2L and RCAP2H, respectively. The HIGH-to-LOW transition of T2EX also causes bit EXF2 in T2CON to be set. EXF2 can be used to generate an interrupt. 10.2.3 AUTOMATIC RELOAD MODE
In the automatic reload mode (see Fig.12) there are two options which are selected by bit EXEN2 in SFR T2CON. If EXEN2 = 0, then a Timer 2 overflow sets TF2 and causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, Timer 2 operates as above, with the added feature that a HIGH-to-LOW transition at the external input T2EX triggers the 16-bit reload and sets EXF2. 10.2.4 BAUD RATE GENERATOR MODE
The baud rate generator mode (see Fig.13) is selected by RCLK = 1 and/or TCLK = 1 in SFR T2CON. Overflows of either Timer 2 or Timer 1 can be used independently for generating baud rates for transmit and receive.
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 capture Timer 2 interrupt RCAP2L RCAP2H EXF2
MLA608
transition detector T2EX PIN control EXEN2
Fig.11 Timer 2 in capture mode.
1998 Apr 07
22
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 reload Timer 2 interrupt RCAP2L RCAP2H
transition detector T2EX PIN control EXEN2
EXF2
MLA609
Fig.12 Timer 2 in automatic reload mode.
handbook, full pagewidth
timer 1 overflow
/2
(note: oscillator frequency is divided by 2 not by 12) OSC 0 1 SMOD TL2 (8 BITS) T2 pin C/T2 = 1 control TR2 reload 1 transition detector T2EX pin control EXEN2 RCAP2L RCAP2H TCLK EXF2 timer 2 interrupt 0 TH2 (8 BITS) 1 0 RCLK
/2
C/T2 = 0
/16
RX clock
/16
TX clock
MGK192
Fig.13 Timer 2 in baud rate generator mode.
1998 Apr 07
23
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
10.3 Watchdog Timer (T3)
P89C738; P89C739
This time interval is determined by the 8-bit reload value that is written into register T3: [ T3 ] x 12 x 2048 Watchdog time interval = ---------------------------------------------f clk The Watchdog Timer can only be reloaded if the condition flag WLE (PCON.4) has been previously set HIGH by software. At the moment the counter is loaded WLE is automatically cleared. In the Idle mode the Watchdog Timer and reset circuitry remain active. The Watchdog Timer is controlled by the Watchdog enable signal EW (EBTCON.1). A HIGH level enables the Watchdog Timer and disables the Power-down mode. A LOW level disables the Watchdog Timer and enables the Power-down mode.
The Watchdog Timer (see Fig.14), consists of an 11-bit prescaler and an 8-bit timer formed by SFR T3. The timer is incremented every 1.5 ms, which is derived from the system clock frequency of 16 MHz by the following f clk formula: f timer = -------------------------------( 12 x 2048 ) The 8-bit timer increments every 12 x 2048 cycles of the on-chip oscillator. When a timer overflow occurs, the microcontroller is reset. The internal reset signal is not inhibited when the external RST pin is kept LOW, e.g. by an external reset circuit. The reset signal drives Ports 1, 2, 3, 4 and 5 outputs into the HIGH state and Port 0 into high-impedance, no matter whether the clock oscillator is running or not. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the processor running out of control.
handbook, full pagewidth
INTERNAL BUS
1/12 fclk
PRESCALER 11-BIT
CLEAR
to reset circuitry (1) TIMER T3 (8-BIT)
LOAD LOADEN
CLEAR
write T3
WLE PCON.4
PD
LOADEN
PCON.1
EW INTERNAL BUS
MBH081
(1) See Fig.21.
Fig.14 Watchdog Timer block diagram.
1998 Apr 07
24
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
11 I/O FACILITIES The P89C738 has 4 and P89C739 has 6 8-bit ports. Ports 0 to 3 are the same as in the 80C51, with the exception of the additional function of Port 1. Port lines P1.0 and P1.1 may be used as inputs for Timer 2, P1.1 may also be used as an additional (third) external interrupt request input. Ports 0, 1, 2, and 3 perform the following alternative functions: Port 0 Provides the multiplexed low-order address and data bus used for expanding the P89C738 with standard memories and peripherals. Port 1 Pins can be configured individually to provide: external interrupt request input (external interrupt 2); external inputs for Timer/counter 2.
P89C738; P89C739
Port 2 Provides the high-order address bus when expanding the P89C738 with external program memory and/or external data memory. Port 3 Pins can be configured individually to provide: external interrupt request inputs (external interrupt 0/1); external inputs for Timer/counter 0 and Timer/counter 1; Serial Port receiver input and transmitter output control signals to read and write external data memory. Bits which are not used for the alternative functions may be used as normal bidirectional I/O pins. The generation or use of a Port 1 or Port 3 pin as an alternative function is carried out automatically by the P89C738 provided the associated SFR bit is HIGH. Otherwise the port pin is held at a logical LOW level.
handbook, full pagewidth
strong pull-up 2 oscillator periods p1
VDD
p2 p3
I/O PIN Q from port latch n I1 input data read port pin INPUT BUFFER
MGG025
Fig.15 I/O buffers in the P89C738; P89C739 (Ports 1, 2, 3, 4 and 5).
1998 Apr 07
25
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
12 FULL DUPLEX SERIAL PORT (UART) The serial port is functionally similar to the implementation in the 8052AH, with the possibility of two different baud rates for receive and transmit with Timer 1 and Timer 2 as baud rate generators. It is full duplex, meaning it can receive and transmit simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time the reception of the second byte is complete, one of the bytes will be lost. The Serial Port receive and transmit registers are both accessed as SFR SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses the physically separate receive register. 12.1 The Serial Port operating modes
P89C738; P89C739
Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). On transmit, the 9th data bit (TB8 in SFR SCON) can be assigned the value of a logic 0 or logic 1. For example, the parity bit (P in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in SFR SCON, while the stop bit is ignored. The baud rate is programmable to either 132 or 164fclk. Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SFR SBUF as a destination register. In Mode 0, reception is initiated by the condition RI = 0 and REN = 1. Reception is initiated by incoming start bit if REN = 1 in the other modes.
The serial port can operate in one of 4 modes: Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are transmitted/received (LSB first). The baud rate is fixed at 112fclk. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). On receive, the stop bit goes into RB8 in SFR SCON. The baud rate is variable.
1998 Apr 07
26
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
12.2 Serial Port Control Register (SCON)
P89C738; P89C739
Table 17 Serial Port Control Register (SFR address 98H) 7 SMO 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 18 Description of SCON bits BIT 7 6 5 SYMBOL SM0 SM1 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be a logic 0. Enables serial reception. Set and cleared by software as required. The 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as required. In Modes 2 and 3, RB8 is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. TI must be cleared by software. Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except: see SM2). RI must be cleared by software. DESCRIPTION These bits are used to select the Serial Port mode; see Table 19.
4 3 2 1
REN TB8 RB8 TI
0
RI
Table 19 Selection of the Serial Port modes SMO 0 0 1 1 SM1 0 1 0 1 MODE Mode 0 Mode 1 Mode 2 Mode 3 DESCRIPTION shift register 8-bit UART 9-bit UART 9-bit UART
1
BAUD RATE
1 f 12 clk
variable
32
or 164fclk
variable
1998 Apr 07
27
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
13 REDUCED POWER MODES Two software selectable modes of reduced power consumption are implemented: Idle and Power-down mode. Idle mode operation permits the interrupt, serial ports and timer blocks to function while the CPU is halted. The following functions remain active during Idle mode: * Timer 0, Timer 1, Timer 2, Watchdog Timer * UART * External interrupt. These functions may generate an interrupt or reset and thus end the Idle mode. The Power-down mode operation freezes the oscillator. and can only be activated by setting the PD bit in the SFR PCON (see Fig.17). 13.1 Idle mode 13.2
P89C738; P89C739
Power-down mode
The instruction that sets PD (PCON.1) is the last executed prior to going into the Power-down mode. The oscillator is stopped. Note that the Power-down mode also can be entered when the watchdog has been disabled. The Power-down mode can be terminated by an external reset in the same way as in the 80C51 or in addition by any one of the two external interrupts, IE0 or IE1 (see Section 9.1). The status of the external pins during Power-down mode is shown in Table 20. If the Power-down mode is activated while in external program memory, the port data that is held in the SFR P2 is restored to Port 2. If the data is a logic 1, the port pin is held HIGH during the Power-down mode by the strong pull-up transistor `p1' (see Fig.15). 13.3 Wake-up from Power-down mode
The instruction that sets IDL (PCON.0) is the last instruction executed in the normal operating mode before Idle mode is activated. Once in the Idle mode, the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during Idle mode. The status of external pins during Idle mode is shown in Table 20. There are three ways to terminate the Idle mode: * Activation of any enabled interrupt will cause IDL (PCON.0) to be cleared by hardware terminating Idle mode. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to PCON.0. The flag bits GF0 (PCON.2) and GF1 (PCON.3) may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. * The second way of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. * The third way of terminating the Idle mode is by internal watchdog reset.
The Power-down mode of the P89C738 can also be terminated by any one of the two external interrupts, IE0 or IE1. A termination with an external interrupt does not affect the internal data memory and does not affect the Special Function Registers (SFRs). This gives the possibility to exit Power-down without changing the port output levels. To terminate the Power-down mode with an external interrupt, IE0 or IE1 must be switched to be level-sensitive and must be enabled. The external interrupt input signal INT0 and INT1 must be kept LOW until the oscillator has restarted and stabilized (see Fig.16). In order to prevent any interrupt priority problems during wake-up, the priority of the desired wake-up interrupt should be higher than the priorities of all other enabled interrupt sources. The instruction following the one that put the device into the Power-down mode will be the first one which will be executed after an interrupt has been serviced.
1998 Apr 07
28
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, full pagewidth
internal timing stopped
C1
C1
C1
C2
Power-down mode oscillator start_up >10 ms >560 ms >10 ms
Idle mode
LCALL
XTAL1, 2 oscillator stopped 32 kHz oscillator stopped 32 kHz oscillator running INT0 INT1
interrupts are polled INT0: 2 cycles INT1: 1 cycle
interrupt routine
MGK195
set external interrupt latch
Fig.16 Wake-up by external interrupt input.
handbook, full pagewidth
XTAL2
XTAL1
OSCILLATOR CLOCK GENERATOR
interrupts, serial port, timer blocks CPU
PD
IDL
MGK194
Fig.17 Internal Idle and Power-down clock configuration.
1998 Apr 07
29
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
13.4 Status of external pins
P89C738; P89C739
Table 20 Status of the external pins during Idle and Power-down modes MODE Idle Power-down MEMORY internal external internal external 13.5 ALE HIGH HIGH LOW LOW PSEN HIGH HIGH LOW LOW PORT 0 port data floating port data floating PORT 1 port data port data port data port data PORT 2 port data address port data port data PORT 3 port data port data port data port data PORT 4 port data port data port data port data PORT 5 port data port data port data port data
Power Control Register (PCON)
Special modes are activated by software via the SFR PCON. PCON is not bit addressable. The reset value of PCON is 00H. Table 21 Power Control Register (SFR address 87H) 7 SMOD 6 ARE 5 RFI 4 WLE 3 GF1 2 GF0 1 PD 0 IDL
Table 22 Description of PCON bits BIT 7 6 5 SYMBOL SMOD ARE RFI DESCRIPTION Double baud rate bit. When set to a logic 1 the baud rate is doubled when Timer 1 is used to generate baud rate, and the Serial Port is used in Modes 1, 2 or 3. AUX-RAM enable bit. When set to a logic 1 the AUX-RAM is disabled, so that all MOVX-instructions access the external data memory. Reduced Radio Frequency Interference bit. When set to a logic 1 the toggling of the ALE pin is prohibited. This bit is cleared on reset. See also Chapters 1 "Features": on EMC and 6 "Pinning information": note 2. Watchdog Load Enable. This flag must be set by software prior to loading the Watchdog Timer (T3). It is cleared when timer T3 is loaded. General-purpose flag bit. Power-down select. Setting this bit activates the Power-down mode. Idle mode select. Setting this bit activates the Idle mode.
4 3 2 1 0 Note
WLE GF1 GF0 PD(1) IDL(1)
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence.
1998 Apr 07
30
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
14 OSCILLATOR CIRCUIT The oscillator circuit of the P89C738 is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between the XTAL 1 and XTAL 2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry (see Fig.19).
P89C738; P89C739
Both are operated in parallel resonance. XTAL 1 is the high gain amplifier input, and XTAL 2 is the output (see Fig.18). To drive the P89C738 externally, XTAL 1 is driven from an external source and XTAL 2 left open-circuit (see Fig.20).
handbook, full pagewidth
to internal timing circuits
VDD
Q2 D1 400 XTAL1 R1 XTAL2
Q1
D2
Q3
PO
Q4
VSS
MGK196
Fig.18 P89C738/P89C739 oscillator internal circuit.
handbook, halfpage
C1 XTAL1 20 pF
handbook, halfpage
NC external oscillator signal XTAL2 CMOS gate
MBK775
XTAL2 XTAL1 VSS
MGK197
C2 20 pF
Fig.19 P89C738/P89C739 oscillator circuit with crystal/ceramic resonator.
Fig.20 Driving the P89C738/P89C739 from an external source.
1998 Apr 07
31
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
15 RESET The reset circuitry for the P89C738 is connected to the reset pin RST. A Schmitt trigger is used at the input for noise rejection. The output of the Schmitt trigger is sampled by the reset circuitry every machine cycle. A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods). The CPU responds by executing an internal reset. During reset ALE and PSEN output are at a HIGH level. In order to perform a correct reset, this level must not be affected by external elements. In the P89C738 the internal reset can also be activated by the Watchdog Timer (T3). If the Watchdog Timer is also used to reset external devices, the usual capacitor arrangement should not be connected to RST pin. Instead, an extra circuit should be used to perform the power-on reset operation. It should be remembered that a timer T3 overflow, if enabled, will force a reset condition to the P89C738 by an internal connection, whether the output RST is tied to LOW or not (see Fig.21).
P89C738; P89C739
The internal reset is executed during the second cycle in which RST is pulled HIGH and is repeated every cycle until RST goes LOW. It leaves the internal registers as shown in Chapter 17. 15.1 Power-on reset
Figure 21 shows the on-chip reset configuration. When VDD is turned on, and provided its rise time does not exceed 10 ms, an automatic reset can be obtained by connecting the RST pin to VDD via a 2.2 F capacitor. When the power is switched on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor charges through the internal resistor (RRST) to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles.
handbook, full pagewidth
VDD + 10 F SCHMITT TRIGGER
RSTOUT RST 8 k RRST GND overflow timer T3 on-chip circuit
RESET CIRCUITRY
POC
MGK198
Fig.21 On-chip reset configuration.
1998 Apr 07
32
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
16 MULTIPLE PROGRAMMING ROM (MTP-ROM) 16.1 Features 16.3.1
P89C738; P89C739
AUTOMATIC PROGRAMMING ALGORITHM
* 64 kbytes electrically erasable internal program memory * Up to 64 kbytes external program memory if the internal program memory is switched off (EA = 0) * Programming and erasing voltage 12 V 5% * Command register architecture - Byte Programming (10 s typical) - Auto chip erase: 5 seconds (typical; including pre-programming time) * Auto-erase and auto-program - DATA polling - Toggle bit * Minimum 100 erase/program cycles * Advanced CMOS MTP memory technology. 16.2 General description
The P89C738 Automatic programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. 16.3.2 AUTOMATIC ERASE ALGORITHM
The P89C738's MTP memories augment EPROM functionality with in-circuit electrical erasure and programming. The P89C738 uses a command register to manage this functionality. P89C738's MTP reliably stores memory contents even after 100 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C738 uses a VPP = 12.0 V 5% supply to perform the auto-erase and auto-program algorithms. 16.3 Automatic programming and Automatic chip erase
The P89C738 Automatic erase algorithm requires the user to only write an erase set-up command and erase command. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the erase operation. Commands are written to the command register. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the P89C738 is designed to support either WE or CE controlled writes. During a system write cycle, addresses are latched on the falling edge of WE or CE whichever occurs last. Data is latched on the rising edge of WE or CE whichever occur first. To simplify the following discussion, the WE pin is used as the write cycle control pin throughout the rest of this text. All set-up and hold times are with respect to the WE signal. 16.4 Command definitions
The P89C738 is byte programmable using the Automatic programming algorithm. The Automatic programming algorithm does not require the system to time out or verify the data programmed. At typical room temperature the chip programming time of the P89C738 is less than 5 seconds. The device may be erased using the Automatic erase algorithm. The Automatic erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of the electrical erase are controlled internally by the device.
When a low voltage is applied to the VPP pin, the contents of the command register is set to a default value: 00H. Applying high voltage to the VPP pin enables read/write operations. Device operations are selected by writing specific data patterns into the command register. Table 23 defines these P89C738 register commands. Table 24 defines the bus operations of the P89C738.
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Philips Semiconductors
Product specification
8-bit Flash microcontrollers
Table 23 Command definitions COMMAND Read identified codes Set-up auto erase/auto chip erase Set-up auto program/program Reset Notes 1. X = don't care. 2. IA = identifier address. 3. ID = data read from location IA during device identification. 4. PA = address of memory location to be programmed. 5. PD = data to be programmed at location. Table 24 P89C738 bus operations READ/WRITE OPERATION Read(2) Standby(5) Write Notes 1. VPPH is the programming voltage specified for the device. VPP(1) VPPH VPPH VPPH CE VIL VIH VIL OE VIL X(6) VIH
P89C738; P89C739
FIRST BUS CYCLE SECOND BUS CYCLE BUS CYCLES OPERATION ADDRESS DATA OPERATION ADDRESS DATA 2 2 2 2 write write write write X(1) X X X 90H 30H 40H FFH read write write write IA(2) X PA(4) X ID(3) 30H PD(5) FFH
WE VIH X VIL
D00 TO D07 data out(3)(4) 3-state data in(3)
2. Manufacturer and device codes are accessed via a command register write sequence. Refer to Table 23. All other addresses are LOW. 3. Data out means that the data is read out from the microcontroller. Data in means that the data is send into the microcontroller from outside. 4. Read operation with VPP = VPPH may access array data (if write command is preceded) or Silicon-ID codes. 5. With VPP at high voltage, the standby current equals IDD + IPP (standby). 6. X can be VIL or VIH.
1998 Apr 07
34
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
16.5 Silicon-ID-Read command
P89C738; P89C739
The set-up of Automatic program is performed by writing 40H to the command register. Once the set-up of the Automatic program operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE pulse. The rising edge of WE also starts the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. The automatic programming operation is completed when the data read on DQ6 stops toggling for two consecutive read cycles and the data on DQ7 and DQ6 are equivalent to data written to these two bits at which time the device returns to the read mode (no program verify command is required; but data can be read out if OE is active LOW). 16.8 Reset command
MTP memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device-codes must be accessible while the device resides in the target system. P89C738 contains a Silicon-ID-Read operation. The operation is initiated by writing 90H into the command register. Following the command write, a read cycle from address 0000H retrieves the manufacturer code: C2H. A read cycle from address 0001H returns the device code: 1AH. 16.6 Set-up of Automatic chip erase and Automatic erase commands
The Automatic chip erase does not require the device to be entirely pre-programmed prior to executing the set-up of Automatic erase command and Automatic chip erase commands. Upon executing the Automatic chip erase command, the device automatically will program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are complete when the data on DQ7 is a logic 1 at which time the device returns to the standby mode. The system is not required to provide any control or timing during these operations. When using the Automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The set-up of the Automatic erase command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. The set-up Automatic erase is performed by writing 30H to the command register. To execute the Automatic chip erase, 30H must be written again to the command register. The automatic chip erase begins on the rising edge of the WE and terminates when the data on DQ7 is a logic 1 and the data on DQ6 stops toggling for two consecutive read cycles, at which time the device returns to the standby mode. 16.7 Set-up of the Automatic program and Program commands
A reset command is provided as a means to safely abort the erase or program command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. Should program-fail or erase-fail happen, two consecutive writes of FFH will reset the device to abort the operation. A valid command must then be written to place the device in the desired state. 16.9 16.9.1 Write operation status Toggle bit DQ6
The P89C738 features a `toggle bit' as a method to indicate to the host system that the Automatic program or erase algorithms are either in progress or completed. While the Automatic program or erase algorithm is in progress, successive attempts to read data from the device will result in DQ6 toggling between a logic 1and a logic 0. Once the Automatic program or erase algorithm is completed, DQ6 will stop toggling and valid data will be read. The toggle bit is valid after the rising edge of the second WE pulse of the two write pulse sequences. Toggle bit appears in Q6, when program or erase is operating.
The set-up of the Automatic program is a command only operation that stages the devices for automatic programming. 1998 Apr 07 35
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
16.9.2 DATA polling DQ7
P89C738; P89C739
16.11 System considerations During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of CE. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. A ceramic capacitor of minimum 0.1 F (high frequency, low inherent inductance) should be used on each device between VDD and VSS, and between VPP and VSS to minimize transient effects. Table 25 Capacitance of pin VPP Tamb = 25 C; fclk = 1.0 MHz SYMBOL CIN COUT PARAMETER input capacitance output capacitance CONDITION VALUE VIN = 0 V VOUT = 0 V 14 pF 16 pF
The P89C738 also features DATA polling as a method to indicate to the host system that the Automatic program or erase algorithms are either in progress or completed. While the Automatic programming algorithm is in operation an attempt to read the device will produce the complement data of the data last written to DQ7. Upon completion of the Automatic programming algorithm an attempt to read the device will produce the true data last written to DQ7. The DATA polling feature is valid after the rising edge of the second WE pulse of the two write pulse sequences. While the Automatic erase algorithm is in operation, DQ7 will read a logic 0 until the erase operation is completed. Upon completion of the erase operation, the data on DQ7 will read a logic 1. The DATA polling feature is valid after the rising edge of the second WE pulse of two write pulse sequences. The DATA polling feature is active during Automatic program or erase algorithms. DATA polling appears in Q7 during programming or erase. 16.10 Write operation Because of the electronic features of the Flash cell, the data to be programmed into Flash should be reversed when programming. In other words, to program 00H the value FFH must be sent to Port 0.
1998 Apr 07
36
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
16.12 Command programming/data programming and erase operation
+5 V VDD A0 to A7 HIGH CE P1 RSTIN P3.3 P0 EA ALE/WE PSEN
P89C738; P89C739
handbook, full pagewidth
PGM command/data VPP LOW pulse LOW OE A15 A8 to A13 A14 0000B
P89C738
XTAL2 4 to 6 MHz XTAL1 VSS
P2.7 P3.5
P2.0 to P2.5 P3.4 P2.6, P3.7, P3.1 and P3.0
MGK199
Fig.22 Automatic programming/erase timing and verification.
Table 26 Pin connections during Automatic programming/erase timing and verification PIN NAME P1.0 to P1.7 P2.0 to P2.5 P3.4 to P3.5 P0.0 to P0.7 P3.3 P2.7 ALE/WE EA/VPP P2.6, P3.7, P3.1 and P3.0 VDD VSS SIGNAL A0 to A7 A8 to A13 A14 to A15 Q0 to Q7 CE OE WE VPP FTEST3 to FTEST0 VDD VSS data input/output Chip Enable input Output Enable input Write Enable pin programming supply voltage Flash Test mode selection power supply voltage (+5 V) ground pin FUNCTION input low-order address bits input high-order address bits
Table 27 DC characteristics during Command programming/data programming and erase operation Tamb = 0 to 70 C; VDD = 5 V 10% (note 1); VPP = 12.0 V 5%; all currents are in RMS unless otherwise noted (sampled, not 100% tested). SYMBOL ILI ILO IDD(stb) IDD(read) IDD(prog) 1998 Apr 07 PARAMETER input leakage current output leakage current supply current standby mode supply current read mode supply current program mode 37 CONDITIONS VIN = VSS to VDD VOUT = VSS to VDD CE = VIH CE = VDD 0.3 V IO = 0 mA; fclk = 1 MHz IO = 0 mA; fclk = 11 MHz - - - - - - - MIN. 10 10 1 100 30 50 50 MAX. UNIT A A mA A mA mA mA
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
SYMBOL IDD(erase) IDD(prog-verify) IDD(erase-verify) IPP(read) IPP(prog) IPP(erase) IPP(prog-verify) IPP(erase-verify) VIL VIH VOL VOH Notes
PARAMETER supply current erase mode supply current program/verify mode supply current erase/verify mode programming supply current read mode programming supply current program mode programming supply current erase mode programming supply current programming/erase mode programming supply current erase/verify mode LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage note 4
CONDITIONS - - - VPP = 12.6 V; note 2 and 3 - - - - -
MIN. 50 50 50
MAX.
UNIT mA mA mA A mA mA mA mA
100 50 50 50 50
-0.5(5) 2.4 - 2.4
0.2VPP - 0.3 V VDD + 0.3(6) 0.45 - V V V
IOL = 2.1 mA IOH = 400 A
1. VDD must be applied before VPP and removed after VPP. 2. VPP must not exceed 14 V including overshoot. 3. The device reliability can be affected when the device is installed or removed while VPP = 12 V. 4. Do not alter VPP either `VIL to 12 V' or `12 V to VIL' when CE = VIL. 5. VIL(min) = -0.5 V for pulse width < 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. Table 28 AC characteristics during command programming, data programming and erase operation Tamb = 0 to 70 C; VDD = 5 V + 10%; VPP = 12 V + 5%; refer to Figs 23 to 27. SYMBOL tsu(Vpp) tsu(OE) Tcy(P) tWP(WE) tWP(WE)H1 tWP(WE)H2 tsu(A) th(A-DATA) tsu(D) th(D) tsu(DATA-CE) tsu(CE) tsu(CE-W) VPP set-up time OE set-up time command programming cycles WE programming pulse width WE programming pulse width HIGH WE programming pulse width HIGH address set-up time address hold time for DATA polling DATA set-up time DATA hold time CE set-up time before DATA polling/toggle bit CE set-up time CE set-up time before command write PARAMETER MIN. 100 100 150 60 20 100 0 0 50 10 100 0 100 - - - - - - - - - - - - - TYP. - - - - - - - - - - - - - MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1998 Apr 07
38
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
SYMBOL th(Vpp) to(dis) tACC(DATA) tE(tot) tP(tot) Notes VPP hold time
PARAMETER output disable time; note 2 DATA polling/toggle bit access time total erase time in auto-chip-erase total programming time in auto-verify - - - 15
MIN. 100 - 35
TYP. - - - -
MAX. ns ns ns s us
UNIT
150 5 -
300
1. CE and OE must be fixed HIGH during VPP transition from `5 to 12 V' or from `12 to 5 V'. 2. to(dis) defined as the time at which the output achieves the open circuit condition and data is no longer driven. 16.12.1 AUTOMATIC PROGRAMMING One byte data is programmed. Verifying in fast algorithm and additional programming by external control are not required because these operations are executed automatically by the internal control circuit. Programming completion can be verified by DATA polling (see Section 16.9.2) and toggle bit (see Section 16.9.1) checking after automatic verify starts. Device outputs DATA during programming and DATA after programming on Q7. Q0 to Q5 are in high-impedance state; Q6 is the toggle bit (see Section 16.9.1). Figure 23 shows the timing waveform. 16.12.2 AUTOMATIC ERASE All the data on the chip is erased. External erase verifying is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs a logic 0 during erasure and a logic 1 after erasure on Q7. Q0 to Q5 are in high-impedance state; Q6 is the toggle bit (see Section 16.9.1). Figure 24 shows the timing waveform.
1998 Apr 07
39
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
16.12.3 TIMING WAVEFORMS
P89C738; P89C739
handbook, full pagewidth
set-up auto program/ program command
auto program and DATA polling
VDD 5 V 12 V VPP
A0 to A15
,,,,,,,
0V tsu(Vpp) WE Tcy(P) CE tsu(OE) tWP(WE) OE tsu(D) th(D) Q7 command in
th(Vpp) address valid tsu(A)
,,
tP(tot)
th(A-DATA)
tWP(WE)H1
tWP(WE)
tsu(CE) tsu(DATA-CE) th(D)
tsu(CE-W)
tsu(D)
tACC(DATA) DATA DATA polling
to(dis) DATA
data in
Q0 to Q5
command in command #40H
data in
DATA
MGK200
Fig.23 Automatic programming timing waveform.
1998 Apr 07
40
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, full pagewidth
set-up auto chip erase/ erase command
auto chip erase and DATA polling
VDD 5 V VPP
12 V 0V
A0 to A15
WE
,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,
tsu(Vpp) th(Vpp) Tcy(P) tE(tot) tsu(OE) tWP(WE) tWP(WE) tWP(WE)H1 tsu(DATA-CE) tsu(D) th(D) tACC(DATA) tsu(CE) tsu(CE-W) tsu(D) th(D) to(dis) command in command in DATA polling
CE
OE
Q7
Q0 to Q5
command in
command in
MGK201
Fig.24 Automatic chip erase timing waveform.
VDD pagewidth handbook, full 5 V 12 V VPP 0V
A0 to A15
WE
,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,
tsu(Vpp) Tcy(P) CE tsu(OE) tWP(WE) OE tsu(D) tWP(WE)H1 th(D) tsu(D) th(D) tWP(WE) command in FFH command in
MGK203
Q0 to Q7
FFH
Fig.25 Reset timing waveform.
1998 Apr 07
41
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
VDD pagewidth handbook, full 5 V 12 V VPP 0V
A0
A1 to A15
,,,,, ,,,,, ,,,,, ,,,,,,,,,,,,,,,,,,
tsu(Vpp) th(Vpp) address valid 0 or 1 tACC Tcy(P) tsu(CE-W) tsu(OE) tWP(WE) tWP(WE)H2 tCE tsu(OE) to(dis) tsu(D) th(D) tOE data out valid C2H or 1AH
MGK202
WE
CE
OE th(D)
Q0 to Q7
command in C0H
Fig.26 VPP = VPPH (high voltage) identification code read timing waveform.
HIGH handbook, full pagewidth WE VPP 12 V CE
OE
toggle bit Q6 during P/E HIGH-Z DATA polling Q7 during P HIGH-Z DATA DATA DATA program/erase complete Q7 during E Q0 to Q5 HIGH-Z DATA DATA
HIGH-Z
DATA polling
DATA
MGK204
Fig.27 Toggle bit, DATA polling timing waveform.
1998 Apr 07
42
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
17 SPECIAL FUNCTION REGISTERS OVERVIEW The P89C738; P89C739 have 30 SFRs available to the user. ADDRESS (HEX) FF F0 EB E0 D0 CD CC CB CA C8 C7 C0 B8 B0 A8 A0 99 98 90 8D 8C 8B 8A 89 88 87 83 82 81 80 Notes 1. X = undefined. 2. Bit addressable register. T3 B(2) EBTCON ACC(2) PSW(2) TH2 TL2 RCAP2H RCAP2L T2CON(2) P5 P4(2) IP0(2) P3(2) IEN0(2) P2 S0BUF S0CON(2) P1(2) TH1 TH0 TL1 TL0 TMOD TCON(2) PCON DPH DPL SP P0(2) NAME RESET VALUE (B)(1) 0000 0000 0000 0000 XXXX XX00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 X000 0000 1111 1111 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 Watchdog Timer B Register Watchdog Timer Control Register Accumulator Program Status Word Timer 2 High byte Register Timer 2 Low byte Register
P89C738; P89C739
FUNCTION
Timer 2 Reload/Capture Register High byte Timer 2 Reload/Capture Register Low byte Timer/Counter 2 Control Register I/O Port Register 5 I/O Port Register 4 Interrupt Priority Register 0 I/O Port Register 3 Interrupt Enable Register 0 I/O Port Register 2 Serial Data Buffer Register 0 Serial Port Control Register 0 I/O Port Register 2 Timer 1 High byte Register Timer 0 High byte Register Timer 1 Low byte Register Timer 0 Low byte Register Timer/Counter Mode Control Register Timer/Counter Control Register Power Control Register Data Pointer High byte Register Data Pointer Low byte Register Stack Pointer I/O Port Register 0
1998 Apr 07
43
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
18 INSTRUCTION SET
P89C738; P89C739
The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz oscillator, 64 instructions execute in 1 s and 45 instructions execute in 2 s. Multiply and divide instructions execute in 4 s. For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 33. Table 29 Instruction set description: Arithmetic operations MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A Rr direct @Ri A Rr direct @Ri DPTR AB AB A Add register to A Add direct byte to A Add indirect RAM to A Add immediate data to A Add register to A with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26, 27 24 3* 35 36, 37 34 9* 95 96, 97 94 04 0* 05 06, 07 14 1* 15 16, 17 A3 A4 84 D4 DESCRIPTION BYTES CYCLES OPCODE (HEX)
1998 Apr 07
44
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
Table 30 Instruction set description: Logic operations MNEMONIC Logic operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate data to A Exclusive-OR A to direct byte Exclusive-OR immediate data to direct byte Clear A Complement A Rotate A left Rotate A left through the carry flag Rotate A right Rotate A right through the carry flag Swap nibbles within A DESCRIPTION
P89C738; P89C739
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1
1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
5* 55 56, 57 54 52 53 4* 45 46, 47 44 42 43 6* 65 66, 67 64 62 63 E4 F4 23 33 03 13 C4
1998 Apr 07
45
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
Table 31 Instruction set description: Data transfer MNEMONIC Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD Note 1. MOV A,ACC is not permitted. A,Rr A,@Ri A,#data Rr,A Rr,direct Rr,#data direct,A direct,Rr direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rr A,direct A,@Ri A,@Ri Move register to A Move indirect RAM to A Move immediate data to A Move A to register Move direct byte to register Move immediate data to register Move A to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Move code byte relative to DPTR to A Move code byte relative to PC to A Move external RAM (8-bit address) to A Move external RAM (16-bit address) to A Move A to external RAM (8-bit address) Move A to external RAM (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange register with A Exchange direct byte with A Exchange indirect RAM with A Exchange LOW-order digit indirect RAM with A DESCRIPTION
P89C738; P89C739
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
E* E5 E6, E7 74 F* A* 7* F5 8* 85 86, 87 75 F6, F7 A6, A7 76, 77 90 93 83 E2, E3 E0 F2, F3 F0 C0 D0 C* C5 C6, C7 D6, D7
A,direct (note 1) Move direct byte to A
DPTR,#data 16 Load data pointer with a 16-bit constant
1998 Apr 07
46
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Table 32 Instruction set description: Boolean variable manipulation, Program and machine control MNEMONIC Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag Move direct bit to carry flag Move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1addr 12 22 32 1addr 02 80 73 60 70 40 50 20 30 10 B5 B4 B* B6, B7 D* D5 00 DESCRIPTION BYTES CYCLES OPCODE (HEX)
Program and machine control ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel A,#data,rel Rr,#data,rel Rr,rel direct,rel addr11 addr16 Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if A is zero Jump if A is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to register and jump if not equal Decrement register and jump if not zero Decrement direct and jump if not zero No operation 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
@Ri,#data,rel Compare immediate to indirect and jump if not equal
1998 Apr 07
47
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
Table 33 Description of the mnemonics in the Instruction set MNEMONIC Data addressing modes Rr direct @Ri #data #data 16 bit addr16 addr11 rel Working registers R0 to R7. 128 internal RAM locations and any special function register (SFR). DESCRIPTION
P89C738; P89C739
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank. 8-bit constant included in instruction. 16-bit constant included as bytes 2 and 3 of instruction. Direct addressed bit in internal RAM or SFR. 16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the 64 kbytes Program Memory address space. 111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction. Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference * * 8, 9, A, B, C, D, E, F. 1, 3, 5, 7, 9, B, D, F. 0, 2, 4, 6, 8, A, C, E.
1998 Apr 07
48
1998 Apr 07 49
Philips Semiconductors
Table 34 Instruction map
8-bit Flash microcontrollers
First hexadecimal character of opcode 0 1 2 3 4 5 6 7 8 9 A B C D E F Note 1. MOV A, ACC is not a valid instruction. 0 NOP JBC bit,rel JB bit,rel JNB bit,rel JC rel JNC rel JZ rel JNZ rel SJMP rel MOV DTPR,#data16 ORL C,/bit ANL C,/bit PUSH direct POP direct MOVX A,@DTPR MOVX @DTPR,A 1 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 2 LJMP addr16 LCALL addr16 RET RETI ORL direct,A ANL direct,A XRL direct,A ORL C,bit ANL C,bit MOV bit,C MOV bit,C CPL bit CLR bit 3 RR A RRC A RL A RLC A ORL direct,#data ANL direct,#data XRL direct,#data JMP @A+DPTR MOVC A,@A+PC MOVC A,@A+DPTR INC DPTR CPL C CLR C
Second hexadecimal character of opcode 4 INC A DEC A ADD A,#data ADDC A,#data ORL A,#data ANL A,#data XRL A,#data MOV A,#data DIV AB SUBB A,#data MUL AB CJNE A,#data,rel SWAP A DA A CLR A CPL A 5 INC direct DEC direct ADD A,direct ADDC A,direct ORL A,direct ANL A,direct XRL A,direct MOV direct,#data MOV direct,direct SUBB A,direct 6 INC @Ri 0 DEC @Ri 0 1 ADD A,@Ri 0 1 ADDC A,@Ri 0 1 ORL A,@Ri 0 1 ANL A,@Ri 0 1 XRL A,@Ri 0 1 MOV @Ri,#data 0 1 MOV direct,@Ri 0 1 SUBB A,@Ri 0 1 MOV @Ri,direct 0 1 CJNE @Ri,#data,rel 0 1 XCH A,@Ri 0 1 XCHD A,@Ri 0 1 MOV A,@Ri 0 1 MOV @Ri,A 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 7 8 9ABCDE INC Rr 123456 DEC Rr 123456 ADD A,Rr 123456 ADDC A,Rr 123456 ORL A,Rr 123456 ANL A,Rr 123456 XRL A,Rr 123456 MOV Rr,#data 123456 MOV direct,Rr 123456 SUB A,Rr 123456 MOV Rr,direct 123456 CJNE Rr,#data,rel 123456 XCH A,Rr 123456 DJNZ Rr,rel 123456 MOV A,Rr 123456 MOV Rr,A 123456 F 7 7 7 7 7 7 7 7 7 7 7 7
CJNE A,direct,rel XCH A,direct DJNZ direct,rel MOV A,direct (1) MOV direct,A
P89C738; P89C739
7 7 7 7
SETB SETB bit C MOVX A,@Ri 0 1 MOVX @Ri,A 0 1
Product specification
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
19 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI Ptot Tstg Tamb supply voltage input voltage on any pin with respect to ground (VSS) total power dissipation storage temperature operating ambient temperature PARAMETER
P89C738; P89C739
MIN. -0.5 -0.5 - -65 0
MAX. +6.5 1 +150 70 V W VDD + 0.5 V
UNIT
C C
20 DC CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = 0 to +70 C; all voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD IDD IDD(id) IDD(pd) Inputs VIL VIL1 VIH VIH1 IIL IITL LOW-level input voltage; except EA LOW-level input voltage EA HIGH-level input voltage (except RST and XTAL1) HIGH-level input voltage RST and XTAL1 input current logic 0 Ports 1, 2, 3, 4 and 5 input current HIGH-to-LOW transition Ports 1, 2, 3, 4 and 5 input leakage current Port 0 and EA VI = 0.45 V VI = 2.0 V -0.5 -0.5 0.2VDD - 1 0.2VDD - 0.3 V V V V A A supply voltage supply current operating supply current Idle mode supply current Power-down mode VDD = 6 V; fclk = 24 MHz; notes 1 and 2 VDD = 6.5 V 10%; fclk = 24 MHz; notes 2 and 3 2 V VPD VDD(max); note 4 4.5 - - - 5.5 60 25 100 V mA mA A PARAMETER CONDITIONS MIN. MAX. UNIT
0.2VDD + 0.9 VDD + 0.5 0.7VDD - - VDD + 0.5 -50 -650
ILI1 Outputs VOL VOL1 VOH
0.45 < VI < VDD
-
10
A
LOW-level output voltage Ports 1, 2, 3, 4 and 5 LOW-level output voltage Port 0, ALE and PSEN HIGH-level output voltage Ports 1, 2, 3, 4 and 5
IOL = 1.6 mA; notes 5 and 6 IOL = 3.2 mA; notes 5 and 6 IOH = -60 A; VDD = 5 V 10% IOH = -25 A IOH = -10 A
- - 2.4 0.75VDD 0.9VDD
0.45 0.45 - - -
V V V V V
1998 Apr 07
50
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
SYMBOL VOH1
PARAMETER HIGH level output voltage Port 0 in external bus mode, ALE, PSEN and RST RST pull-down resistor capacitance of input buffer
CONDITIONS IOH = -800 A; VDD = 5 V 10% IOH = -300 A IOH = -80 A; note 7 test frequency = 1 MHz; Tamb = 25 C 2.4
MIN. - - - 100 10 0.75VDD 0.9VDD 40 -
MAX.
UNIT V V V k pF
RRST CI/O Notes
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; EA = RST = Port 0 = VDD; the Watchdog Timer is disabled (by the external reset). 2. IDD(max) at other frequencies can be derived from Fig.28. 3. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns; VIL = VSS +0.5 V; VIH = VDD -0.5 V; XTAL2 not connected; the Watchdog Timer is disabled; EA = RST = VSS; Port 0 = P1.6 = P1.7 = VDD. 4. The Power-down current is measured with all output pins disconnected; XTAL2 not connected; Watchdog Timer is disabled; EA = RST = XTAL1 = VSS; Port 0 = P1.6 = P1.7 = VDD. 5. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW-level output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases (capacitive loading >100 pF) the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable to provide ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: a) Maximum IOL per port pin: 10 mA. b) Maximum IOL per 8-bit port: Port 0 = 26 mA; Ports 1, 2, 3, 4 and 5 = 15 mA. c) Maximum total IOL for all output pins: 71 mA. d) If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. Capacitive loading on Port 0 and Port 2 may cause the HIGH-level output voltage on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing.
1998 Apr 07
51
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, halfpage
30
MGK205
IDD (mA) maximum active mode 20 typical active mode
10 maximum Idle mode
0 0 4 8 12
typical Idle mode 16 20 frequency (MHz)
Fig.28 IDD as function of frequency; valid only within frequency specifications of the device under test.
21 AC CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = 0 to +70 C; tclk(min) = 63 ns; Cl = 100 pF for Port 0, ALE and PSEN; Cl = 80 pF for all other outputs unless otherwise specified; tclk(min) = 1/fclk(max); fclk = clock frequency; tclk = clock period. 12 MHz SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. External program memory tLHLL tAVLL tLLAX tLLIV ALE pulse duration address set-up time to ALE address hold time after ALE 127 28 48 - - - 233 85 8 28 - - - - 150 43 23 21 - - - - 95 35 10 10 - - - - 55 2tclk - 40 tclk - 55 tclk - 35 - - - - 4tclk - 100 ns ns ns ns MIN. MAX. 16 MHz 24 MHz 40 MHz VARIABLE CLOCK(1) UNIT
time from ALE to - valid instruction input time from ALE to 43 control pulse PSEN control pulse duration PSEN time from PSEN to valid instruction input 205 -
tLLPL
-
23
-
28
-
10
-
tclk - 40
-
ns
tPLPH tPLIV
- 145
143 -
- 83
90 -
- 55
60 -
- 25
3tclk - 45 -
-
ns
3tclk - 105 ns
1998 Apr 07
52
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
12 MHz SYMBOL tPXIX PARAMETER -
16 MHz -
24 MHz -
40 MHz -
VARIABLE CLOCK(1) UNIT MIN. 0 - MAX. ns
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. input instruction hold time after PSEN input instruction float delay after PSEN address to valid instruction input PSEN to address float time 0 0 0 0
tPXIZ
-
59
-
38
-
8
-
15
-
tclk - 25
ns
tAVIV tPLAZ
- -
312 10
- -
208 10
- -
125 10
- 5
65 -
- -
5tclk - 105 10
ns ns
External data memory tLHLL tAVLL tLLAX tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL ALE pulse duration address set-up time to ALE address hold time after ALE RD pulse duration WR pulse duration RD to valid data input data hold time after RD data float delay after RD 127 28 48 400 400 - 0 - - - - - - 252 - 97 517 585 300 - 85 8 28 275 275 - 0 - - - 138 120 - - - - - 148 - 55 350 398 238 - 43 15 21 149 149 - 0 - - - 74 91 - - - - - 118 - 40 183 209 174 - 35 10 10 120 120 - 0 - - - 60 70 - - - - - 30 - 15 110 130 90 - 2tclk - 40 tclk - 55 tclk - 35 - - - ns ns ns ns ns ns ns ns ns ns ns ns
6tclk - 100 - 6tclk - 100 - - 0 - - - 3tclk - 50 5tclk - 165 - 2tclk - 70 8tclk - 150 9tclk - 165 3tclk + 50
time from ALE to - valid data input address to valid data input -
time from ALE to 200 RD or WR time from 203 address to RD or WR time from RD or WR HIGH to ALE HIGH data valid to WR transition 43
4tclk - 130 -
tWHLH
123
23
103
21
66
10
40
tclk - 40
tclk + 40
ns
tQVWX
23
-
3
-
21
-
5
-
tclk - 60
-
ns
1998 Apr 07
53
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
12 MHz SYMBOL tQVWH tWHQX tRLAZ Note PARAMETER - - 0
16 MHz - - 0
24 MHz - - 0
40 MHz - - 0
VARIABLE CLOCK(1) UNIT MIN. 7tclk - 150 - tclk - 50 - - 0 MAX. ns ns ns
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. data set-up time before WR data hold time after WR address float delay after RD 433 33 - 288 13 - 200 21 - 125 5 -
1. The operating frequency is limited to: 3.5 MHz fclk 40 MHz. Table 35 External clock drive XTAL1 VARIABLE CLOCK SYMBOL fclk tCLCL tCHCX tCLCX tCLCH tCHCL tCY PARAMETER MIN. clock frequency clock period high time low time rise time fall time cycle time (tCY = 12tclk) 3.5 63 20 20 - - 0.75 40 833 tclk - tCLCX tclk - tCHCX 20 20 10 MAX. MHz ns ns ns ns ns s UNIT
handbook, full pagewidth
t CHCX V IH1 0.8 V V IH1 0.8 V
t CLCH V IH1 0.8 V t CLCX t CLCL V IH1 0.8 V
t CHCL
MLA856
Fig.29 External clock drive XTAL1.
1998 Apr 07
54
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, full pagewidth
VDD - 0.5
0.2VDD + 0.9 0.2VDD - 0.1
MGK209
0.45 V
a. Output waveform.
handbook, full pagewidth
VLOAD + 0.1 V VLOAD VLOAD - 0.1 V
timing reference points
VOH - 0.1 V VOL + 0.1 V
MGK210
b. Float waveform
AC testing inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0. Timing measurements are taken at 2.0 V for a logic 1 and 0.8 V for a logic 0, see Fig.30a. The float state is defined as the point at which a Port 0 pin sinks 3.2 mA or sources 400 A at the voltage test levels, see Fig.30b.
Fig.30 AC testing input.
1998 Apr 07
55
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, full pagewidth
one machine cycle S1 P1 P2 XTAL1 INPUT S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2
one machine cycle S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2
ALE dotted lines are valid when RD or WR are active PSEN
only active during a read from external data memory only active during a write to external data memory
RD
WR
external program memory fetch
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
read or write of external data memory
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
data output or data input
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15 or Port 2 out
address A8 - A15
PORT OUTPUT
old data
new data
PORT INPUT sampling time of I/O port pins during input (including INT0 and INT1) SERIAL PORT CLOCK
MGA180
Fig.31 Instruction cycle timing.
1998 Apr 07
56
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
21.1 Serial Port characteristics
P89C738; P89C739
Table 36 Serial Port timing: Shift Register mode VDD = 5 V 10%; VSS = 0 V; Tamb = 0 to 70 C; load capacitance = 80 pF. 12 MHz OSCILLATOR MIN. tXLXL tQVXH tXHQX tXHDX tXHDV Serial Port clock cycle time output data set-up to clock rising edge input data hold after clock rising edge clock rising edge to input data valid 1 700 0 - - - - - 700 MAX. VARIABLE OSCILLATOR UNIT MIN. 12tclk 10tclk - 133 2tclk - 117 0 - - - - - 10tclk - 133 MAX. s ns ns ns ns
SYMBOL
PARAMETER
output data hold after clock rising edge 50
handbook, full pagewidth INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
t XLXL CLOCK t XHQX OUTPUT DATA t QVXH
WRITE TO SBUF INPUT DATA t XHDV
VALID VALID
t XHDX
SET TI
VALID VALID VALID VALID VALID
VALID
CLEAR RI
MGA179
SET RI
Fig.32 Shift register mode timing.
1998 Apr 07
57
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
21.2 Timing waveforms
P89C738; P89C739
handbook, full pagewidth
tLHLL
ALE tAVLL tLLPL tPLIV PSEN tPLAZ tLLAX PORT 0 A0 to A7 tLLIV tAVIV PORT 2 A0 to A15 A8 to A15
MGK206
tPLPH
tPXIZ tPXIX instr in A0 to A7
Fig.33 External program memory read cycle.
handbook, full pagewidth
ALE
tWHLH PSEN tLLWL RD tRLAZ tAVLL PORT 0 tLLAX A0 to A7 from RI or DPL tAVWL tAVDV PORT 2 P2.0 to P2.7 or A8 to A15 from DPH A0 to A15 from PCH
MGK207
tLLDV tRLRH
tRLDV tRHDX data in
tRHDZ
A0 to A7 from PCL
instr in
Fig.34 External data memory read cycle.
1998 Apr 07
58
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, full pagewidth
ALE
tWHLH PSEN
tAVWL tLLWL tWLWH
WR tQVWX tAVLL PORT 0 tLLAX A0 to A7 from RI or DPL data output A0 to A7 from PCL instr in tWHQX
PORT 2
P2.0 to P2.7 or A8 to A15 from DPF
A0 to A15 from PCH
MGK208
Fig.35 External data memory write cycle.
21.3
Timing symbol naming conventions
* P = PSEN * Q = output data * R = RD signal * t = time * V = valid * W = WR signal * X = no longer a valid logic level * Z = float. Examples: tAVLL = time for address valid to ALE LOW tLLPL = time for ALE LOW to PSEN LOW.
Each timing symbol has five characters. The first character is always a `t' (= time). The remaining four characters of the symbol (typed in subscript), depending on their relative positions, indicate the name of a signal or the logical status of that signal. The designations are as follows: * A = address * C = clock * D = input data * H = logic level HIGH * I = instruction (program memory contents) * L = Logic level LOW or ALE
1998 Apr 07
59
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
22 PACKAGE OUTLINES DIP40: plastic dual in-line package; 40 leads (600 mil)
P89C738; P89C739
SOT129-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 40 21 MH wM (e 1)
pin 1 index E
1
20
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 15.24 0.60
L 3.60 3.05 0.14 0.12
ME 15.80 15.24 0.62 0.60
MH 17.42 15.90 0.69 0.63
w 0.254 0.01
Z (1) max. 2.25 0.089
52.50 51.50 2.067 2.028
14.1 13.7 0.56 0.54
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015AJ EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1998 Apr 07
60
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT319-1
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vM A 20 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.50 0.35 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Apr 07
61
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
23 SOLDERING 23.1 Introduction
P89C738; P89C739
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 23.3.2 WAVE SOLDERING
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). 23.2 23.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
23.3.2.1
PLCC
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 23.2.2 REPAIRING SOLDERED JOINTS
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners.
23.3.2.2
QFP
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 23.3 23.3.1 PLCC and QFP REFLOW SOLDERING
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners.
Reflow soldering techniques are suitable for all PLCC and QFP packages. The choice of heating method may be influenced by larger plastic PLCC and QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the 1998 Apr 07 62
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
23.3.2.3 Method (PLCC and QFP)
23.3.3
P89C738; P89C739
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 24 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 25 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Apr 07
63
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
455104/1200/02/pp64
Date of release: 1998 Apr 07
Document order number:
9397 750 03529

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